Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Increases in storage density have been facilitated in various ways, including increasing the density of memory cells on a chip enabled by manufacturing developments, and transitioning from single-level flash memory cells to multi-level flash memory cells, so that two or more bits can be stored by each flash memory cell.
Generally, non-volatile memory devices, such as flash memory devices, include a plurality die. The amount of program-erase (PE) cycles that the plurality of die within a same non-volatile memory device can sustain before being considered operationally defunct varies significantly (e.g., by a factor of three). As such, a non-volatile memory device's endurance is, typically, only as robust as its weakest die. Thus, a method for managing the varying endurance capabilities of die within a non-volatile memory device is desired.